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rev.1.30 may 25, 2007 page 1 of 69 rej03b0168-0130 r8c/26 group, r8c/27 group single-chip 16-bit cmos mcu 1. overview these mcus are fabricated using a hi gh-performance silicon gate cmos proc ess, embedding the r8c/tiny series cpu core, and are packaged in a 32-pin molded-plastic lqfp. it implements sophi sticated instructions for a high level of instruction efficiency. with 1 mbyt e of address space, they are capable of executing instructi ons at high speed. furthermore, the r8c/27 group has on-chip data flash (1 kb 2 blocks). the difference between the r8c/26 group and r8c/27 group is only the presence or absence of data flash. their peripheral functions are the same. 1.1 applications electronic household appliances, offi ce equipment, audio equipment, c onsumer products, automotive, etc. rej03b0168-0130 rev.1.30 may 25, 2007 j and k versions are under development. specif ications may be changed without prior notice.
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 2 of 69 rej03b0168-0130 1.2 performance overview table 1.1 outlines the functions and specifications for r8c/26 group and table 1.2 outl ines the functions and specifications for r8c/27 group. notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d, k version if d, k version functions are to be used. table 1.1 functions and specifications for r8c/26group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) (other than k version) 62.5 ns (f(xin) = 16 mhz, vcc = 3.0 to 5.5 v) (k version) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) (n, d version) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.3 product information for r8c/26 group peripheral functions ports i/o ports: 25 pins, input port: 3 pins led drive ports i/o ports: 8 pins (n, d version) timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rc: 16 bits 1 channel (input capture and out put compare circuits) timer re: with real-time clock and compare match function (for j, k version, compare match function only.) serial interfaces 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) start-on-reset selectable interrupts internal: 15 sour ces, external: 4 sources, software: 4 sources, priority levels: 7 levels clock generation circuits 3 circuits ? xin clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has a frequency adjustment function ? xcin clock generation circuit (32 khz) (n, d version) ? real-time clock (timer re) (n, d version) oscillation-stopped detector xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) (other than k version) vcc = 3.0 to 5.5 v (f(xin) = 16 mhz) (k version) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) (n, d version) current consumption (n, d version) typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 100 times operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d, j version) (2) , -40 to 125 c (k version) (2) package 32-pin molded-plastic lqfp
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 3 of 69 rej03b0168-0130 notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d, k version if d, k version functions are to be used. table 1.2 functions and specifications for r8c/27 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) (other than k version) 62.5 ns (f(xin) = 16 mhz, vcc = 3.0 to 5.5 v) (k version) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) (n, d version) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.4 product information of r8c/27 group peripheral functions ports i/o ports: 25 pins, input port: 3 pins led drive ports i/o ports: 8 pins (n, d version) timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rc: 16 bits 1 channel (input capture and output compare circuits) timer re: with real-time clock and compare match function (for j, k version, compare match function only.) serial interfaces 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d conver ter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) start-on-reset selectable interrupts internal: 15 sources, external: 4 sources, software: 4 sources, pr iority levels: 7 levels clock generation circuits 3 circuits ? xin clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has a frequency adjustment function ? xcin clock generation circuit (32 khz) (n, d version) ? real-time clock (timer re) (n, d version) oscillation-stopped detector xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) (other than k version) vcc = 3.0 to 5.5 v (f(xin) = 16 mhz) (k version) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) (n, d version) current consumption (n, d version) typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 10,000 times (data flash) 1,000 times (program rom) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d, j version) (2) , -40 to 125 c (k version) (2) package 32-pin molded-plastic lqfp
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 4 of 69 rej03b0168-0130 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c/tiny series cpu core a/d converter (10 bits 12 channels) uart or clock synchronous serial i/o (8 bits 2 channels) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. 3. xcin, xcout can be used only for n or d version. i 2 c bus interface or clock synchronous serial i/o with chip select (8 bits 1 channel) lin module (1 channel) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout (3) timers timer ra (8 bits) timer rb (8 bits) timer rc (16 bits 1 channel) timer re (8 bits) 8 port p0 8 port p1 6 port p3 1 3 port p4 2 port p5 peripheral functions
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 5 of 69 rej03b0168-0130 1.4 product information table 1.3 lists product information for r8c/26 group an d table 1.4 lists product information for r8c/27 group. (d): under development notes: 1. these versions are under development. specif ications may be changed without prior notice. 2. the user rom is programmed before shipment. table 1.3 product information for r8c/26 group current of may. 2007 part no. rom capacity ram capacity package type remarks r5f21262snfp 8 kbytes 512 bytes plqp0032gb-a n version r5f21264snfp 16 kbytes 1 kbyte plqp0032gb-a r5f21265snfp 24 kbytes 1.5 kbytes plqp0032gb-a r5f21266snfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21262sdfp 8 kbytes 512 bytes plqp0032gb-a d version r5f21264sdfp 16 kbytes 1 kbyte plqp0032gb-a r5f21265sdfp 24 kbytes 1.5 kbytes plqp0032gb-a r5f21266sdfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21264jfp (d) 16 kbytes 1 kbyte plqp0032gb-a j version (1) r5f21266jfp (d) 32 kbytes 1.5 kbytes plqp0032gb-a r5f21264kfp (d) 16 kbytes 1 kbyte plqp0032gb-a k version (1) r5f21266kfp (d) 32 kbytes 1.5 kbytes plqp0032gb-a r5f21262snxxxfp (d) 8 kb ytes 512 bytes plqp0032gb-a n version (1) factory programming product (2) r5f21264snxxxfp (d) 16 kb ytes 1 kbyte plqp0032gb-a r5f21265snxxxfp (d) 24 kbyt es 1.5 kbytes plqp0032gb-a r5f21266snxxxfp (d) 32 kbyt es 1.5 kbytes plqp0032gb-a r5f21262sdxxxfp (d) 8 kb ytes 512 bytes plqp0032gb-a d version (1) r5f21264sdxxxfp (d) 16 kb ytes 1 kbyte plqp0032gb-a r5f21265sdxxxfp (d) 24 kbyt es 1.5 kbytes plqp0032gb-a r5f21266sdxxxfp (d) 32 kbyt es 1.5 kbytes plqp0032gb-a r5f21264jxxxfp (d) 16 kb ytes 1 kbyte plqp0032gb-a j version (1) r5f21266jxxxfp (d) 32 kbyt es 1.5 kbytes plqp0032gb-a R5F21264KXXXFP (d) 16 kb ytes 1 kbyte plqp0032gb-a k version (1) r5f21266kxxxfp (d) 32 kbyt es 1.5 kbytes plqp0032gb-a
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 6 of 69 rej03b0168-0130 figure 1.2 part number, memory size, and package of r8c/26 group part no. r 5 f 21 26 6 s n xxx fp package type: fp: plqp0032gb-a rom number classification n: operating ambient temperature -20c to 85c (n version) d: operating ambient temperature -40c to 85c (d version) j: operating ambient temperature -40c to 85c (j version) k: operating ambient temperature -40c to 125c (k version) s: low-voltage version (other no symbols) rom capacity 2: 8 kb 4: 16 kb 5: 24 kb 6: 32 kb r8c/26 group r8c/tiny series memory type f: flash memory version renesas mcu renesas semiconductor
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 7 of 69 rej03b0168-0130 (d): under development notes: 1. these versions are under development. specif ications may be changed without prior notice. 2. the user rom is programmed before shipment. table 1.4 product information for r8c/27 group current of may. 2007 part no. rom capacity ram capacity package type remarks program rom data flash r5f21272snfp 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a n version r5f21274snfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a r5f21275snfp 24 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21276snfp 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21272sdfp 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a d version r5f21274sdfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a r5f21275sdfp 24 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21276sdfp 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21274jfp (d) 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a j version (1) r5f21276jfp (d) 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21274kfp (d) 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a k version (1) r5f21276kfp (d) 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21272snxxxfp (d) 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a n version (1) factory programming product (2) r5f21274snxxxfp (d) 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a r5f21275snxxxfp (d) 24 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21276snxxxfp (d) 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21272sdxxxfp (d) 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a d version (1) r5f21274sdxxxfp (d) 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a r5f21275sdxxxfp (d) 24 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21276sdxxxfp (d) 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21274jxxxfp (d) 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a j version (1) r5f21276jxxxfp (d) 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21274kxxxfp (d) 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a k version (1) r5f21276kxxxfp (d) 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 8 of 69 rej03b0168-0130 figure 1.3 part number, memory size, and package of r8c/27 group part no. r 5 f 21 27 6 s n xxx fp package type: fp: plqp0032gb-a rom number classification n: operating ambient temperature -20c to 85c (n version) d: operating ambient temperature -40c to 85c (d version) j: operating ambient temperature -40c to 85c (j version) k: operating ambient temperature -40c to 125c (k version) s: low-voltage version (other no symbols) rom capacity 2: 8 kb 4: 16 kb 5: 24 kb 6: 32 kb r8c/27 group r8c/tiny series memory type f: flash memory version renesas mcu renesas semiconductor
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 9 of 69 rej03b0168-0130 1.5 pin assignments figure 1.4 shows pin assignments (top view). figure 1.4 pin assignments (top view) notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. 3. xcin, xcout can be used only for n or d version. 4. confirm the pin 1 position on the package by referring to the package dimensions. r8c/26 group, r8c/27 group xin/xcin/p4_6 (3) xout/xcout/p4_7 (1, 3) vss/avss reset vcc/avcc p3_7/trao/sso/rxd1/(txd1) (2) mode p4_5/int0/(rxd1) (2) p1_7/traio/int1 p3_6/(txd1)/(rxd1)/(int1) (2) p3_5/scl/ssck/(trciod) (2) p1_0/ki0/an8 p1_4/txd0 vref/p4_2 p1_3/ki3/an11/(trbo) p3_3/int3/ssi/trcclk p1_1/ki1/an9/trcioa/trctrg p1_2/ki2/an10/trciob p0_3/an4 p0_2/an5 p0_1/an6 p0_0/an7/(txd1) (2) p0_7/an0 p0_6/an1 p0_5/an2/clk1 p1_5/rxd0/(traio)/(int1) (2) p1_6/clk0/(ssi) (2) p5_3/trcioc p5_4/trciod p3_1/trbo p3_4/sda/scs/(trcioc) (2) p0_4/an3/treo 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 578 1234 6 plqp0032gb-a (32p6u-a) (top view)
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 10 of 69 rej03b0168-0130 1.6 pin functions table 1.5 lists pin functions. i: input o: output i/o: input and output table 1.5 pin functions type symbol i/o type description power supply input vcc, vss i apply 2.2 v to 5.5 v (j, k version are 2.7 v to 5.5 v) to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss i power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provided for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. to use an exte rnal clock, input it to the xin pin and leave the xout pin open. xin clock output xout o xcin clock input (n, d version) xcin i these pins are provided for xc in clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output (n, d version) xcout o int interrupt input int0 , int1 , int3 iint interrupt input pins key input interrupt ki0 to ki3 i key input interrupt input pins timer ra trao o timer ra output pin traio i/o timer ra i/o pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o sharing output-compare output / input-capture input / pwm / pwm2 output pins timer re treo o timer re output pin serial interface clk0, clk1 i/o clock i/o pin rxd0, rxd1 i receive data input pin txd0, txd1 o transmit data output pin i 2 c bus interface scl i/o clock i/o pin sda i/o data i/o pin clock synchronous serial i/o with chip select ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter a/d converter an0 to an11 i analog input pins to a/d converter i/o port p0_0 to p0_7, p1_0 to p1_7, p3_1, p3_3 to p3_7, p4_5, p5_3, p5_4 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. p1_0 to p1_7 also function as led drive ports. (n, d version) input port p4_2, p4_6, p4_7 i input-only ports
r8c/26 group, r8c/27 group 1. overview rev.1.30 may 25, 2007 page 11 of 69 rej03b0168-0130 notes: 1. this can be assigned to the pin in parentheses by a program. 2. xcin, xcout can be used only for n or d version. table 1.6 pin name information by pin number pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface clock synchronous serial i/o with chip select i 2 c bus interface a/d converter 1 p3_5 (trciod) (1) ssck scl 2 p3_7 trao rxd1/ (txd1) (1) sso 3 reset 4 xout/xcout (2) p4_7 5 vss/avss 6 xin/xcin (2) p4_6 7vcc/avcc 8mode 9 p4_5 int0 (rxd1) (1) 10 p1_7 int1 traio 11 p3_6 (int1 ) (1) (txd1)/ (rxd1) (1) 12 p3_1 trbo 13 p5_4 trciod 14 p5_3 trcioc 15 p1_6 clk0 (ssi) (1) 16 p1_5 (int1 ) (1) (traio) (1) rxd0 17 p1_4 txd0 18 p1_3 ki3 (trbo) an11 19 p1_2 ki2 trciob an10 20 vrff p4_2 21 p1_1 ki1 trcioa/ trctrg an9 22 p1_0 ki0 an8 23 p3_3 int3 trcclk ssi 24 p3_4 (trcioc) (1) scs sda 25 p0_7 an0 26 p0_6 an1 27 p0_5 clk1 an2 28 p0_4 treo an3 29 p0_3 an4 30 p0_2 an5 31 p0_1 an6 32 p0_0 (txd1) (1) an7
r8c/26 group, r8c/27 group 2. ce ntral processing unit (cpu) rev.1.30 may 25, 2007 page 12 of 69 rej03b0168-0130 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/26 group, r8c/27 group 2. ce ntral processing unit (cpu) rev.1.30 may 25, 2007 page 13 of 69 rej03b0168-0130 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is analogous to a0. a1 can be combined with a0 to be used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register th at indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0.
r8c/26 group, r8c/27 group 2. ce ntral processing unit (cpu) rev.1.30 may 25, 2007 page 14 of 69 rej03b0168-0130 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupt are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/26 group, r8c/27 group 3. memory rev.1.30 may 25, 2007 page 15 of 69 rej03b0168-0130 3. memory 3.1 r8c/26 group figure 3.1 is a memory map of r8c/26 group. the r8c/ 26 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0ffffh. for example, a 16-kbyte internal rom area is allocated addr esses 0c000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocated highe r addresses beginning with address 00400h. for example, a 1-kbyte internal ram area is allocated addresses 00400h to 007ffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.1 memory map of r8c/26 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch note: 1. the blank regions are reserved. do not access locations in these regions. fffffh 0ffffh 0yyyyh internal rom (program rom) expanded area 0xxxh part number internal rom internal ram size size r5f21262snfp, r5f21262sdfp, r5f21262snxxxfp, r5f21262sdxxxfp r5f21264snfp, r5f21264sdfp, r5f21264jfp, r5f21264kfp, r5f21264snxxxfp, r5f21264sdxxxfp, r5f21264jxxxfp, R5F21264KXXXFP r5f21265snfp, r5f21265sdfp r5f21265snxxxfp, r5f21265sdxxxfp r5f21266snfp, r5f21266sdfp, r5f21266jfp, r5f21266kfp, r5f21266snxxxfp, r5f21266sdxxxfp, r5f21266jxxxfp, r5f21266kxxxfp 8 kbytes 16 kbytes 24 kbytes 32 kbytes 0e000h 0c000h 0a000h 08000h 512 bytes 1 kbyte 1.5 kbytes 1.5 kbytes 005ffh 007ffh 009ffh 009ffh address 0yyyyh address 0xxxxh
r8c/26 group, r8c/27 group 3. memory rev.1.30 may 25, 2007 page 16 of 69 rej03b0168-0130 3.2 r8c/27 group figure 3.2 is a memory map of r8c/27 group. the r8c/ 27 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower ad dresses, beginning with a ddress 0ffffh. for example, a 16-kbyte internal rom area is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram area is allocated higher addresses, beginning with address 00400h. for example, a 1-kbyte internal ram is allocated addresses 00400h to 007ffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks wh en interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/27 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset fffffh 0ffffh 0yyyyh 00400h 002ffh 00000h internal rom (program rom) expanded area internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch internal rom (data flash) (1) notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. 0xxxxh 02400h 02bffh part number internal rom internal ram size address 0yyyyh size address 0xxxxh r5f21272snfp, r5f21272sdfp, r5f21272snxxxfp, r5f21272sdxxxfp r5f21274snfp, r5f21274sdfp, r5f21274jfp, r5f21274kfp, r5f21274snxxxfp, r5f21274sdxxxfp, r5f21274jxxxfp, r5f21274kxxxfp r5f21275snfp, r5f21275sdfp, r5f21275snxxxfp, r5f21275sdxxxfp r5f21276snfp, r5f21276sdfp, r5f21276jfp, r5f21276kfp, r5f21276snxxxfp, r5f21276sdxxxfp, r5f21276jxxxfp, r5f21276kxxxfp 8 kbytes 16 kbytes 24 kbytes 32 kbytes 0e000h 0c000h 0a000h 08000h 512 bytes 1 kbyte 1.5 kbytes 1.5 kbytes 005ffh 007ffh 009ffh 009ffh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 17 of 69 rej03b0168-0130 4. special function registers (sfrs) an sfr (special function register) is a control register fo r a peripheral function. tables 4.1 to 4.7 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the csproini bit in the ofs register is set to 0. 3. in j, k version these regions are reserved. do not access locations in these regions. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (2) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 (3) fra4 when shipping 002ah 002bh high-speed on-chip oscillator control register 6 (3) fra6 when shipping 002ch 002dh 002eh 002fh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 18 of 69 rej03b0168-0130 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. (n, d version) software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this r egister. (j, k version) software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1 and hardware reset. 4. power-on reset, voltage monitor 0 reset or the lvd0on bit in the ofs register is set to 0, and hardware reset. 5. (n, d version) software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. (j, k version) software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3. 6. (n, d version) software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this r egister. (j, k version) these regions are reserved. do not access locations in these regions. 7. the lvd1on bit in the ofs register is set to 1 and hardware reset. 8. power-on reset, voltage monitor 1 reset, or the lvd1on bit in the ofs register is set to 0 and hardware reset. 9. selected by the iicsel bit in the pmr register. address register symbol after reset 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 ?n, d version 00h (3) 00100000b (4) ?j, k version 00h (7) 01000000b (8) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (5) vw1c ? n, d version 00001000b ? j, k version 0000x000b (7) 0100x000b (8) 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h voltage monitor 0 circuit control register (6) vw0c 0000x000b (3) 0100x001b (4) 0039h 003fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer re interrupt control register treic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu / iic interrupt control register (9) ssuic / iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 006fh 0070h 007fh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 19 of 69 rej03b0168-0130 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 00b9h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 00bah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 00bbh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 00bch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 00bdh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 00beh ss transmit data register / iic bus transmit data register (2) sstdr / icdrt ffh 00bfh ss receive data register / iic bus receive data register (2) ssrdr / icdrr ffh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 20 of 69 rej03b0168-0130 table 4.4 sfr information (4) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. in j, k version these regions are reserved. do not access locations in these regions. address register symbol after reset 00c0h a/d register ad xxh 00c1h xxh 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 00h 00e1h port p1 register p1 00h 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 00h 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 00h 00e9h port p5 register p5 00h 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h pin select register 1 pinsr1 00h 00f6h pin select register 2 pinsr2 00h 00f7h pin select register 3 pinsr3 00h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 00h 00feh port p1 drive capacity control register (2) p1drr 00h 00ffh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 21 of 69 rej03b0168-0130 table 4.5 sfr information (5) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. in j, k version these regions are reserved. do not access locations in these regions. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register (2) trehr 00h 011bh timer re day of week data register (2) trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re clock source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011111b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 22 of 69 rej03b0168-0130 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh
r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.1.30 may 25, 2007 page 23 of 69 rej03b0168-0130 table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a pr ogram. use a flash programmer to write to it. address register symbol after reset 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh ffffh option function select register ofs (note 2)
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 24 of 69 rej03b0168-0130 5. electrical characteristics 5.1 n, d version notes: 1. v cc = 2.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the typical values when average output current is 100 ms. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c500mw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.2 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ??? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ??? 80 ma i oh(peak) peak output ?h? current except p1_0 to p1_7 ??? 10 ma p1_0 to p1_7 ??? 40 ma i oh(avg) average output ?h? current except p1_0 to p1_7 ??? 5ma p1_0 to p1_7 ??? 20 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol(peak) ?? 160 ma i ol(sum) average sum output ?l? currents sum of all pins i ol(avg) ?? 80 ma i ol(peak) peak output ?l? currents except p1_0 to p1_7 ?? 10 ma p1_0 to p1_7 ?? 40 ma i ol(avg) average output ?l? current except p1_0 to p1_7 ?? 5ma p1_0 to p1_7 ?? 20 ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz f (xcin) xcin clock input oscillation frequency 2.2 v v cc 5.5 v 0 ? 70 khz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected 3.0 v v cc 5.5 v ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.7 v v cc 5.5 v ?? 10 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.2 v v cc 5.5 v ?? 5mhz
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 25 of 69 rej03b0168-0130 notes: 1. av cc = 2.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. figure 5.1 ports p0, p1, and p3 to p5 timing measurement circuit table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bits ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb 10-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 5 lsb 8-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.2 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold v ref = av cc = 2.7 to 5.5 v 0.25 ? 10 mhz with sample and hold v ref = av cc = 2.7 to 5.5 v 1 ? 10 mhz without sample and hold v ref = av cc = 2.2 to 5.5 v 0.25 ? 5mhz with sample and hold v ref = av cc = 2.2 to 5.5 v 1 ? 5mhz p0 p1 p3 p4 p5 30pf
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 26 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/26 group 100 (3) ?? times r8c/27 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 27 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 8. ? 40 c for d version. 9. the data hold time includes time that the po wer supply is off or the clock is not supplied. table 5.5 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature ? 20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 28 of 69 rej03b0168-0130 figure 5.2 time delay until suspend notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. 4. this parameter shows the voltage detection level when the power supply drops. the voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 v. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. table 5.6 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 5.7 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (4) 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 5.8 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 29 of 69 rej03b0168-0130 notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if ? 20 c t opr 85 c, maintain t w(por1) for 3,000 s or more if ? 40 c t opr < ? 20 c. figure 5.3 reset circuit electrical characteristics table 5.9 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit of hardware manual for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit of hardware manual for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2v external power v cc t rth t rth
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 30 of 69 rej03b0168-0130 notes: 1. v cc = 2.2 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. these standard values show when the fra1 register value after reset is assumed. 3. these standard values show when the corrected value of the fra6 register is written to the fra1 register. note: 1. v cc = 2.2 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature supply voltage dependence v cc = 4.75 v to 5.25 v 0 c t opr 60 c (2) 39.2 40 40.8 mhz v cc = 3.0 v to 5.5 v ? 20 c t opr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 v to 5.5 v ? 40 c t opr 85 c (2) 38.4 40 41.6 mhz v cc = 2.7 v to 5.5 v ? 20 c t opr 85 c (2) 38 40 42 mhz v cc = 2.7 v to 5.5 v ? 40 c t opr 85 c (2) 37.6 40 42.4 mhz v cc = 2.2 v to 5.5 v ? 20 c t opr 85 c (3) 35.2 40 44.8 mhz v cc = 2.2 v to 5.5 v ? 40 c t opr 85 c (3) 34 40 46 mhz v cc = 5.0 v 10% ? 20 c t opr 85 c (2) 38.8 40 40.8 mhz v cc = 5.0 v 10% ? 40 c t opr 85 c (2) 38.4 40 40.8 mhz ? value in fra1 register after reset 08h (3) ? f7h (3) ? ? oscillation fr equency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to ? 1 ? +0.3 ? mhz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 5.11 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 5.12 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 31 of 69 rej03b0168-0130 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.13 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 32 of 69 rej03b0168-0130 figure 5.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 33 of 69 rej03b0168-0130 figure 5.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 34 of 69 rej03b0168-0130 figure 5.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 35 of 69 rej03b0168-0130 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.14 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 36 of 69 rej03b0168-0130 note: 1. v cc = 4.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 20 mh z, unless otherwise specified. table 5.15 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p1_0 to p1_7, xout i oh = ? 5 ma v cc ? 2.0 ? v cc v i oh = ? 200 av cc ? 0.5 ? v cc v p1_0 to p1_7 drive capacity high i oh = ? 20 ma v cc ? 2.0 ? v cc v drive capacity low i oh = ? 5 ma v cc ? 2.0 ? v cc v xout drive capacity high i oh = ? 1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = ? 500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except p1_0 to p1_7, xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v p1_0 to p1_7 drive capacity high i ol = 20 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ??? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 37 of 69 rej03b0168-0130 table 5.16 electrical characteristics (2) [vcc = 5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 17 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz no division ? 10 15 ma xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 10 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 38 of 69 rej03b0168-0130 table 5.17 electrical characteristics (3) [vcc = 5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 75 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.2 ? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.8 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.2 ? a
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 39 of 69 rej03b0168-0130 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) [v cc = 5 v] figure 5.8 xin input and xcin input timing diagram when v cc = 5 v figure 5.9 traio input timing diagram when v cc = 5 v table 5.18 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.19 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 40 of 69 rej03b0168-0130 i = 0 or 1 figure 5.10 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 external interrupt inti input timing diagram when v cc = 5 v table 5.20 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.21 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 1 v cc = 5 v inti input t w(inl) t w(inh) i = 0, 1, 3 v cc = 5 v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 41 of 69 rej03b0168-0130 note: 1. v cc =2.7 to 3.3 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 10 mh z, unless otherwise specified. table 5.22 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p1_0 to p1_7, xout i oh = ? 1 ma v cc ? 0.5 ? v cc v p1_0 to p1_7 drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout drive capacity high i oh = ? 0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except p1_0 to p1_7, xout i ol = 1 ma ?? 0.5 v p1_0 to p1_7 drive capacity high i ol = 5 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3 v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3 v ??? 4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 42 of 69 rej03b0168-0130 table 5.23 electrical characteristics (4) [vcc = 3 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 59ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 70 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.8 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.0 ? a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 43 of 69 rej03b0168-0130 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) [v cc = 3 v] figure 5.12 xin input and xcin input timing diagram when v cc = 3 v figure 5.13 traio input timing diagram when v cc = 3 v table 5.24 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.25 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 44 of 69 rej03b0168-0130 i = 0 or 1 figure 5.14 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.15 external interrupt inti input timing diagram when v cc = 3 v table 5.26 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.27 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 3 v i = 0, 1, 3
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 45 of 69 rej03b0168-0130 note: 1. v cc = 2.2 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 5 mhz, unless otherwise specified. table 5.28 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p1_0 to p1_7, xout i oh = ? 1 ma v cc ? 0.5 ? v cc v p1_0 to p1_7 drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout drive capacity high i oh = ? 0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except p1_0 to p1_7, xout i ol = 1 ma ?? 0.5 v p1_0 to p1_7 drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxin feedback resistance xin ? 5 ? m ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 46 of 69 rej03b0168-0130 table 5.29 electrical characteristics (6) [vcc = 2.2 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 100 230 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 100 230 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 25 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 22 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 20 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 1.8 ? a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 47 of 69 rej03b0168-0130 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at t opr = 25 c) [v cc = 2.2 v] figure 5.16 xin input and xcin input timing diagram when v cc = 2.2 v figure 5.17 traio input timing diagram when v cc = 2.2 v table 5.30 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input ?h? width 90 ? ns t wl(xin) xin input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.31 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 48 of 69 rej03b0168-0130 i = 0 or 1 figure 5.18 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.19 external interrupt inti input timing diagram when v cc = 2.2 v table 5.32 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.33 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 1000 (1) ? ns t w(inl) inti input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 2.2 v i = 0, 1, 3
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 49 of 69 rej03b0168-0130 5.2 j, k version notes: 1. v cc = 2.7 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. the typical values when average output current is 100 ms. table 5.34 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage -0.3 to 6.5 v v i input voltage -0.3 to v cc + 0.3 v v o output voltage -0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c300mw 85 c t opr 125 c125mw t opr operating ambient temperature -40 to 85 (j version) / -40 to 125 (k version) c t stg storage temperature -65 to 150 c table 5.35 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.7 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? -60 ma i oh(peak) peak output ?h? current ?? -10 ma i oh(avg) average output ?h? current ?? -5 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol(peak) ?? 60 ma i ol(peak) peak output ?l? currents ?? 10 ma i ol(avg) average output ?l? current ?? 5ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v (other than k version) 0 ? 20 mhz 3.0 v v cc 5.5 v (k version) 0 ? 16 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v (other than k version) 0 ? 20 mhz 3.0 v v cc 5.5 v (k version) 0 ? 16 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected (other than k version) ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected ?? 10 mhz j and k versions are under development. specif ications may be changed without prior notice.
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 50 of 69 rej03b0168-0130 notes: 1. av cc = 2.7 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, t he a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. figure 5.20 ports p0, p1, and p3 to p5 timing measurement circuit table 5.36 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bits ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.7 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold 0.25 ? 10 mhz with sample and hold 1 ? 10 mhz p0 p1 p3 p4 p5 30pf
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 51 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 3. endurance to guarantee all electrical c haracteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple pr ogramming operations, the act ual erasure count can be reduc ed by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failur e rate information should contact their renesas technical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.37 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/26 group 100 (3) ?? times r8c/27 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 52 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 3. endurance to guarantee all electrical c haracteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple pr ogramming operations, the act ual erasure count can be reduc ed by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failur e rate information should contact their renesas technical support representative. 8. 125 c for k version. 9. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.38 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature -40 ? 85 (8) c ? data hold time (9) ambient temperature = 55 c20 ?? year
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 53 of 69 rej03b0168-0130 figure 5.21 time delay until suspend notes: 1. the measurement condition is v cc = 2.7 v to 5.5 v and t opr = -40 to 85 c (j version) / -40 to 125 c (k version). 2. hold v det2 > v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again af ter setting the vca26 bit in the vca2 register to 0. 4. this parameter shows the voltage detection level when the power supply drops. the voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 v. notes: 1. the measurement condition is v cc = 2.7 v to 5.5 v and t opr = -40 to 85 c (j version) / -40 to 125 c (k version). 2. hold v det2 > v det1 . 3. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 4. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. table 5.39 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (2, 4) 2.70 2.85 3.0 v ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s vccmin mcu operating voltage minimum value 2.70 ?? v table 5.40 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level (2) 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (3) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 54 of 69 rej03b0168-0130 notes: 1. the measurement condition is t opr = ? 40 to 85 c (n version) / ? 40 to 125 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 1 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 res pectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if ? 20 c t opr 125 c, maintain t w(por1) for 3,000 s or more if ? 40 c t opr < ? 20 c. figure 5.22 reset circuit el ectrical characteristics table 5.41 power-on reset circuit, voltage monitor 1 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 1 reset valid voltage 0 ? v det1 v t rth external power v cc rise gradient (2) 20 ?? mv/msec v det1 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det1 (3) v por2 32 1 f oco-s 32 1 f oco-s 2.7v t rth t rth external power v cc notes: 1. when using the voltage monitor 1 digital filter, ensure that the voltage is within the mcu operation voltage range (2.7 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit of hardware manual for details. 3. v det1 indicates the voltage detection level of the voltage detection 1 circuit. refer to 6. voltage detection circuit of hardware manual for details.
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 55 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v, t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. these standard values show when the fra1 register value after reset is assumed. note: 1. v cc = 2.7 to 5.5 v, t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.7 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit st abilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.42 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature supply voltage dependence v cc = 4.75 v to 5.25 v 0 c t opr 60 c (2) 39.2 40 40.8 mhz v cc = 3.0 v to 5.5 v ? 20 c t opr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 v to 5.5 v ? 40 c t opr 85 c (2) 38.4 40 41.6 mhz v cc = 3.0 v to 5.5 v ? 40 c t opr 125 c (2) 38 40 42 mhz v cc = 2.7 v to 5.5 v ? 40 c t opr 125 c (2) 37.6 40 42.4 mhz ? value in fra1 register after reset 08h ? f7h ? ? oscillation frequency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to ? 1 ? +0.3 ? mhz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 5.43 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 40 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 5.44 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabiliz ation during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 56 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v, v ss = 0 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.45 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time ?? 1.5t cyc + 100 ns t or ssi slave out open time ?? 1.5t cyc + 100 ns
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 57 of 69 rej03b0168-0130 figure 5.23 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 58 of 69 rej03b0168-0130 figure 5.24 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 59 of 69 rej03b0168-0130 figure 5.25 i/o timing of clock sy nchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 60 of 69 rej03b0168-0130 notes: 1. v cc = 2.7 to 5.5 v, v ss = 0 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.26 i/o timing of i 2 c bus interface table 5.46 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 61 of 69 rej03b0168-0130 note: 1. v cc = 4.2 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), f(xin) = 20 mhz, unless otherwise specified. table 5.47 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except xout i oh = -5 ma v cc ? 2.0 ? v cc v i oh = -200 av cc ? 0.3 ? v cc v xout drive capacity high i oh = -1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5v ?? -5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 62 of 69 rej03b0168-0130 table 5.48 electrical characteristics (2) [vcc = 5 v] (t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 17 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz (j version) low-speed on-chip oscillator on = 125 khz no division ? 10 15 ma xin clock off high-speed on-chip oscillator on foco = 20 mhz (j version) low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 10 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 75 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 60 a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.8 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.2 ? a xin clock off, t opr = 125 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 4.0 ? a
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 63 of 69 rej03b0168-0130 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) [v cc = 5 v] figure 5.27 xin input timing diagram when v cc = 5 v figure 5.28 traio input timing diagram when v cc = 5 v table 5.49 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns table 5.50 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 64 of 69 rej03b0168-0130 i = 0 or 1 figure 5.29 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.30 external interrupt inti input timing diagram when v cc = 5 v table 5.51 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.52 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 1 v cc = 5 v inti input t w(inl) t w(inh) i = 0, 1, 3 v cc = 5 v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 65 of 69 rej03b0168-0130 note: 1. v cc =2.7 to 3.3 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), f(xin) = 10 mhz, unless otherwise specified. table 5.53 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except xout i oh = -1 ma v cc ? 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = -50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except xout i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0,clk1, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3v ?? -4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 66 of 69 rej03b0168-0130 table 5.54 electrical characteristics (4) [vcc = 3 v] (t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 59ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 70 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 55 a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a xin clock off , t opr = 125 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 3.8 ? a
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 67 of 69 rej03b0168-0130 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) [v cc = 3 v] figure 5.31 xin input timing diagram when v cc = 3 v figure 5.32 traio input timing diagram when v cc = 3 v table 5.55 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns table 5.56 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/26 group, r8c/27 group 5. electrical characteristics rev.1.30 may 25, 2007 page 68 of 69 rej03b0168-0130 i = 0 or 1 figure 5.33 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.34 external interrupt inti input timing diagram when v cc = 3 v table 5.57 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.58 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 3 v i = 0, 1, 3
rev.1.30 may 25, 2007 page 69 of 69 rej03b0168-0130 r8c/26 group, r8c/27 group package dimensions package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c
a - 1 revision history r8c/26 group, r8c/27 group datasheet rev. date description page summary 0.10 nov 14, 2005 ? first edition issued 0.20 feb 06, 2006 2, 3 table 1.1 functions and specifications for r8c/26group and table 1.2 functions and specifications for r8c/27 group; minimum instruction execution time and supply voltage revised 9 table 1.6 pin name information by pin number; ?xout? ?xout/xcout? and ?xin? ?xin/xcin? revised 18 table 4.4 sfr information (4); 00feh: ?drr? ?p1drr? revised 19 table 4.5 sfr information (5); -0119h: ?timer re minute data register / compare register? ?timer re minute data regist er / compare data register? -011ah: ?timer re time data register? ?timer re hour data register? -011bh: ?timer re day data register? ?timer re day of week data register? revised 22 to 45 5. electrical characteristics added 1.00 nov 08, 2006 all pages ?preliminary? deleted 2 table 1.1 revised 3 table 1.2 revised 4 figure 1.1 revised 5 table 1.3 revised 6 table 1.4 revised 7 figure 1.4 revised 9 table 1.6 revised 15 table 4.1; ? 001ch: ?00h? ?00h, 10000000b? revised ? 000fh: ?000xxxxxb? ?00x11111b? revised ? 0029h: ?high-speed on-chip oscillator cont rol register 4, fra4, when shipping? added ? 002bh: ?high-speed on -chip oscillator control register 6, fra6, when shipping? added ? 0032h: ?00h, 01000000b? ?00h, 00100000b? revised ? 0038h: ?00001000b, 01001001b? ?0000x000b, 0100x001b? revised ? note3 and 4 revised; note6 added 18 table 4.4; ? 00e0h, 00e1h, 00e5h, 00e8h, 00e9h: ?xxh? ?00h? revised ? 00fdh: ?xx00000000b? ?00h? revised 22 table 5.2 revised 23 figure 5.1 title revised 24 table 5.4 revised 25 table 5.5 revised 26 figure 5.2 title revised and table 5.7 note4 added revision history r8c/26 group, r8c/27 group datasheet
a - 2 revision history r8c/26 group, r8c/27 group datasheet 1.00 nov 08, 2006 27 table 5.9, figure 5.3 revised and table 5.10 deleted 28 table 5.10, table 5.11 revised 34 table 5.15 revised 35 table 5.16 revised 36 table 5.17 revised 39 table 5.22 revised 40 table 5.23 revised 44 table 5.29 revised 47 package dimensions; ?diagrams sh owing the latest...website.? added 1.10 nov 29, 2006 all pages ?j, k version? added 1 1 ?j and k versions are under development...notice.? added 1.1 revised 2 table 1.1 revised 3 table 1.2 revised 4 figure 1.1 note3 added 5 table 1.3, figure 1.2 revised 6 table 1.4, figure 1.3 revised 7 figure 1.4 note3 added 8 table 1.5 revised 9 table 1.6 note2 added 13 figure 3.1 revised 14 figure 3.2 revised 15 table 4.1; ?0000h to 003fh? ?0000h to 002fh? revised ? note3 added 16 table 4.2; ?0040h to 007fh? ?0030h to 007fh? revised ? 0032h, 0036h: ?after reset? is revised ? 0038h: note revised ? notes 2, 5, 6 revised and note 7, 8 added 19 table 4.5 note2 added 28 table 5.10 revised 48 to 66 5.2 j, k version added 1.20 jan 17, 2007 18 table 4.4 note2 added 1.30 may 25, 2007 2 table 1.1 revised 3 table 1.2 revised 5 table 1.3 revised 6 figure 1.2 revised 7 table 1.4 revised 8 figure 1.3 revised 9 figure 1.4 note4 added 15 figure 3.1 part number revised rev. date description page summary
a - 3 revision history r8c/26 group, r8c/27 group datasheet 1.30 may 25, 2007 16 figure 3.2 part number revised 30 table 5.10 revised 53 table 5.39 note4 added 55 table 5.42 revised rev. date description page summary
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